Каморка

J-Squared Technologies

is proud to present a FREE seminar on Assertion Based Verification

Events
--------------------------------------------------------------------------------

Assertion Based Verification (ABV)
Wilsonville, OR (Portland) on Tuesday Feb 20, 2007
Time: 09:00-11:30
Register Now

Assertion Based Verification (ABV)
Redmond ,WA (Seattle) on Wednesday Feb 21, 2007
Time: 09:00-11:30
Register Now

Assertion Based Verification (ABV)
Vancouver, BC (Coquitlam) on Thursday Feb 22, 2007
Time: 09:00-11:30
Register Now


Perhaps one of the most difficult tasks of any design team is determining whether or not their design has been adequately tested. While many teams utilize test plans which outline specific functionality to be exercised, they have not had the ability to collect objective metrics directly from their simulation environment. It is also difficult to ascertain whether tests that appear to run successfully in fact violate protocols or assumptions in other parts of the design that are not the focus of those tests.

Assertion Based Verification (ABV)

DATES: Feb 20-22
TIMES: 09:00-11:30

LOCATION(S):
Wilsonville, OR.
Redmond, WA
Vancouver, BC


Register Now

Assertion Based Verification (ABV) is a verification methodology that addresses these issues. This methodology utilizes "assertions" and "coverage points", which allow designers to describe intended design behavior and critical scenarios that must be exercised. These properties that are evaluated within the simulation environment to ensure that no properties have been violated and that all coverage points have been reached.

The SystemVerilog language provides a framework for describing assertions and coverage points. This new verification language has already been embraced by some of the leading technology firms around the world, and is now a common element of the tool environment of many design with significant verification challenges.

This seminar is an introduction to how assertions and coverage points are described using SystemVerilog, with examples of how to use them to improve your verification environment today. Discover the benefits of Assertion Based Verification for increased error detection and isolation as well as overall debug productivity

Beverages and pastries will be supplied.

Looking forward to seeing you there.

Sincerely,


Jason Johnson
J-Squared Technologies Inc.

--------------------------------------------------------------------------------

email: jasonj@jsquarednw.com
phone: (360)727-0036
web: http://www.jsquared.com

// One more ... //


Mentor Graphics & J-Squared Technologies Inc.
FREE HyperLynx & PADS Seminar






Productivity Enhancements in a High Speed Design Flow


Mentor Graphics

Mentor Graphics offers a complete suite of tools for analysis and verification. These solutions provide the flexibility to meet the needs of the designer at any stage and are unmatched by any other tool set on the market today. From easy-to-use analysis tools to fully integrated design, analysis and verification capabilities, Mentor Graphics gives you the tools that solve your most critical needs.


Register Now




J-Squared Technologies Inc. and Mentor Graphics invite you to attend a FREE Seminar. The topic of this event is "Productivity Enhancements in a High Speed Design Flow".


Overview

Design for high-speed challenges such as timing, signal integrity, and EMI has become a standard part of most PCB design processes. It is no longer sufficient to rely on conservative design rules ("rules of thumb") and then hope that the design will work on the first prototype iteration. An effective design process will eliminate design iterations that will get you to production faster and in a cost effective manner.

An effective design process involves:


Early design exploration to evaluate new devices and to define constraints
Early involvement with board manufactures, manufacturing (assembly), procurement and mechanical engineering
Routing strategies that adhere to the defined constraints
Design verification to ensure that it will function per design specifications

When and Where



Coquitlam, BC

Thursday, March 8th, 9:00am-11:30am
Best Western Coquitlam Inn Convention Centre
319 North Road
Coquitlam, BC. V3K 3V8


Seating is limited, so please RSVP soon if you would like to attend. Also, if you have peers who may be interested, please pass this on as our invite list is not very large, so they may not have received this email. We will have breakfast snacks and beverages so that no one should go hungry.

I look forward to seeing you there.

Sincerely,


Jason Johnson
Office: (360)727-0036
Mobile: (360)281-6388




Productivity Enhancements in a High Speed Design Flow
Who Should Attend


Engineers and Engineering Managers who design board-level systems
Anyone concerned with high-speed PCB design -- even if you're not a signal integrity expert
Users of competitive tool such as P-CAD, CADSTAR, OrCAD, and Protel

What You Will Learn
This session will take you through a typical PCB design process and highlight areas where high- speed considerations should be made. This seminar will address:

Analysis of driver strength, net topology and termination, as well as their effects on signal integrity and EMC
Constraint definition for achieving desired performance metrics
Routing strategies that will help you adhere to high-speed constraints on an already complex board
Verification of signal integrity and EMC
Effective debug techniques to resolve any problems that are found


EVENT INFO



March 8, 2007



9:00AM-11:30AM



Coquitlam, BC



FREE Seminar



Register Now



SPONSORED BY



J-Squared Technologies Inc.






Register Now